I’m trying to learn the ropes of PCB design, but am hoping to get some feedback on this:
I calculated the minimum trace width for several components on my PCB, and for one of them this turned turned out to be around 20mils (it’s the trace connecting a D cell that will supply 800mA for an Electron). However, when I want to route the traces towards the pads of one of my surface-mounted components, I’m nowhere near able to get such wide traces without overlap - the widest I can go is about 8mil before I start getting clearance issues.
What should I be doing here? Is it ok to leave the trace width at 8mils around the pads and widen it away from the pad (as I did in the image)?
Glad yo see you are trying your hand at PCB layout. You are asking a very reasonable question. Being a relative newbie at this (only 4 years) I can remember having some of these questions:
Pick a simple package. In your post, it looks like you are using a Ball Grid Array package. This is not the easiest way to start. Sometimes, you can find a SOIC or TSSOP package for your chip which will be easier to solder and troubleshoot.
By PCB standards, 20 mils is a huge trace which I might use for power distribution across an entire board. For a BGA package like this, you are likely not driving much current so a much smaller trace will be fine and easier to route.
The company which will manufacture your boards should give you design rules even in electronic format to help you understand their minimum trace width and clearance standards and check your design against them before you send the board for production. I use OSHPark and you can find there rules for (looks like you are using EAGLE) here: http://docs.oshpark.com/design-tools/eagle/design-rules-files/
The trace width is primarily about the amount of current you can pass without loss and excess heating. If you were looking to put a significant current through a trace, you should use one of the many trace width calculators on the web such as this one: http://docs.oshpark.com/design-tools/eagle/design-rules-files/
I use OSHPark’s prototype service which is 2 layers (traces are not inside the FR4) and 1 oz copper. Using this example, a 20mil trace could carry 750mA with only a 20F Temp rise over 70F ambient temp over a 1 inch trace. Your package will likely only generate 1/100 that current so a much thinner trace will be fine.
Good luck in your efforts, I hope this was helpful.
I agree with @chipmc. A BGA isn’t a good choice for beginners if you can get a SOIC for the same device. If your device is a power management device that will deliver significant current, then 20-50 mil traces isn’t uncommon. However, signal traces should be kept as small as possible to minimize EMI, cross-talk, capacitance introduction, etc. Pick your board house before you start your layout and check their recommendations for board layout. OSHPark has a design rules package that you can download for all the major CAD programs. I use Eagle and when you start a board, you click on DRC and load the “OSHPart 2-layer” rules. Eagle automatically starts flagging clearance and other layout issues. So for signal traces, OSHPark can do a minimum of 6 mils. I usually go with 10 mil. When laying out power, I go with something larger based on the max current I expect and whatever a trace calculator tells me is the minimum.
Autodesk has a good “10 PCB Routing Tips” write up. It includes alot of EE 101 lessons such as don’t use right angles in your traces. Rather use a bend or chamfer to flatten out the corner. I would not change the trace width as you have when entering your package. It is OK to use a large trace to carry your power out to multiple packages and then run a smaller trace out to each chip. For example, you could have a 20 mil trace that breaks out into two 10 mil traces at the peripheral packages. However, if the high-current is originating from a package, such as a voltage regulator, it should be the full trace width right up to the regulator output. For example, if you have a 1117 voltage regulator putting out 1A, then right from that output pad, start with a large 30-40 mil trace. Only when you get down to a peripheral (that pulls much less current) can you reduce to a smaller trace width. In this example (work in progress) I have a large 40 mil trace carrying the full power but each package pulls from the main trace with a 10 mil trace (smaller traces circled in blue).
I’m planning to make use of a PCBA service for this, so I won’t be soldering anything myself (I want to have a 100-200 PCB quantity)
The component from the image actually is supposed to convert a 3.2-3.6V output from the battery to a steady 3.6V. Since the Electron can use up to 800mA, shouldn’t this mean that at some point 800mA may run through these traces?
I have already downloaded the DRU file from the manufacturer (Seeedstudio) and applied them to my board - I’m indeed using Eagle
Thanks for taking the time to reply to my post, it’s very helpful info
You are correct, you could have 800mA on a trace. If you can’t fit the proper trace width, you may want to bump up to a 2oz copper board (2 ounces of copper per square foot of board). OSHPark offers a 2oz service. Most boards are only 1 oz by default. The more copper, the higher the current it can carry. The downfall of the higher copper weight is that you can’t do super small traces. However, I don’t believe that 1oz vs 2oz poses much issue in that regard as OSHPark does not have special limitations for the 2oz service. If you plan for 1 oz copper and 2 inches of trace length, this trace calculator says you need 12 mil. If you bump up to 2oz copper, you only need 6 mil.
The 2 typical ways this is done is the way you have done it. Called necking down. The other is to use x vias around the pad and connect the heavier trace on the bottom side.
One thing I see that you should start to avoid, and that is to stop using traces with 90 deg. angles.
Thanks for all the help! I will have a look at it tomorrow and figure out what I want to do with this. I just realized that the component does have two pads (each) for Boostin and GND, which should split the current that flows through these pads in half (if I understand it correctly)… the only concern would be P$4 which is going to run directly to the Electron and does need to support 800mA in a single trace
I didn’t pay that close attention to pin names first go around. Being that there are 2 gnd pads and 2 Boostin pins your going to want to keep the traces that connect to them as close to the same length as possible. So something like this would be a better option.
Hey! I was really hoping someone would be able to take a few minutes to go through my PCB and highlight any important errors I made. I’m sure I made many, but I’m learning the ropes of it and would appreciate some feedback
I am planning to add some silkscreen and a ground plane later. Please be advised that GND36 and GND are not supposed to be connected, so I left them separated.
The small cutouts are mounting holes. The extra-large thru-holes are for a battery holder (bottom two) and for for soldering two big stranded wires (top two). Trace widths:
@Vitesze, I wouldn’t call them errors, but maybe you are trying to keep everything on the top layer?
For example, I see you use the blue layer to jump over the red layer.
If the trace is going to a through hole connector, you can start the run from the connector on the blue layer and reduce the number of vias.
I would add the ground layer now instead of later. This will simplify the routing and avoid some of the jumps you have. Keep in mind that you can have a plane on the blue layer and run traces as well.
I don’t know if the 4 pin connectors have to have that pinout and location. In some cases you can simplify the routing by changing the connector pinout, and/or switching their position.
That’s just what I see, but there may be other factors depending on what the circuits do.
I do try to keep as much top-layer as possible - it just makes things a bit organized, but that’s a personal thing. Also I’m not yet fully sure if these components actually are surface-mounted, or if they penetrate towards the bottom layer. But I will try to reduce the vias as much as possible once I find out - I figure less vias = cheaper pcb.
The 4-pinout has to be in that location + orientation - the component that goes on it is pretty bulky - the only other possible location I could put it at would be all the way on the right side of the PCB
PCB probably appears huge - I do need the mounting holes though to create stability, and I will add a few more components in the future.
Very clean looking board. Sparsely populated though… as long as you can afford, or require the extra board space, then it’s OK. I try to minimize board area to save money at the board house but I’m not constrained by an enclosure or anything; rather, I just need to design enough space to contain all the components. I agree with @Pescatore that some of your vias to the bottom plane don’t need to jump back up to the top plane. But if you’re not doing ADC or RF stuff, then any noise or signal degradation from vias is probably a non-issue. I see why you were having a problem with that booster in the BGA package… it looks like that whole package is no bigger than a 0805 SMD component. I can’t believe a package like that is rated for close to 1A. You might have to deal with heat from that device so keep other components (and external objects) away and add copper pour on both sides to dissipate heat (just talking out loud here as I don’t know the ratings for it.)
One thing I learned recently is to leave all my GND pads unconnected. Then when I’m almost finished, I place a polygon for a copper fill on both top and bottom planes and name them GND. The program automatically connects all the GND pads. All you might have to do is a little “via stitching” to connect the 2 GND planes where your traces create islands in the fill. By doing the GND plane, your signal traces don’t have to jump as much to avoid ground traces. When you do a 4 layer board, you can have both a ground and supply plane so your traces don’t have to avoid them as much, if at all.
The extra board space is for adding the mounting holes - without it, it would be difficult to secure the PCB in place in my current enclosures. Also in the future I probably want to add a few more components on it anyway. I’ll check how much the extra board space actually matters price-wise with my fab house.
I will re-do the bottom vias tomorrow.
The booster indeed is super-small - but does actually intake this many Amps. I used an existing breakout board of it successfully, and simply copied the Eagle files of it for my own PCB. I’ll try the via trick to separate heat between top/bottom traces.
As far as stitching goes you did a great job, although you really don’t need to have a ground plane on both sides for this. One side will do just fine.
Might I make a couple comments. It would be better to jump one wire (GND) than to jump 6.
Some things are just good to get in the habit of, probably wont matter for your design, but when you run traces along the same length its a good idea to shift the opposite layer off by one grid spacing. When you place them over one another like I have pointed out one wire can induce its signal onto the other wire on the other side.
So I would just do a regular copper pour, instead of ground plane for the bottom side? What’s the downside from having two ground planes like this, when you don’t need it?
Ah, good point. Initially I thought it’d be impossible for me to jump that GND trace as it’s 40mils wide, but I can do the multiple-via trick for it.
Thanks for the signal induction tip, didn’t know that, will fix it now.
For a board as like this one, a single ground plane is just fine. Though what you have done using 2 is ok as well. One of the the downsides of having 2 ground planes on a 2 layer board is that your traces brake it up to much, so its like whats the point.
