@satishgn I haven’t read the whole thing yet, but this jumped out at me:
The dual slow interleaved ADC mode is intended for the conversion of one channel. ADC1
and ADC2 convert the selected channel alternately with a period of 14 ADC clock cycles.
The channel is thus converted every 14 clock cycles. Each ADC converts the channel every
28 ADC clock cycles. The conversion can be started by external trigger or by software and
the conversion results of ADC1 and ADC2 are stored into ADC1’s data register (32-bit
format).
The maximum allowed sampling time is 14 ADC clock cycles to avoid any overlap with the
next conversion. This means that the only allowed sampling times are 1.5, 7.5 and 13.5
cycles.
Yet we still have it set to 41.5.
EDIT: Sounds like the effective sampling rate using two ADCs at 13.5 is still about half as good impedance wise as one ADC set to 41.5. However the sampling rate is higher. I guess for a small percentage of users this would be beneficial. Most would want a rock solid reading.