See this post... it really doesn't. But the theory was if you need to sample at a fast rate, you are using two A/D converters on the same input in an interleaved fashion which effectively doubles the impedance (or so) that you would get if you used the same sample rate with only one A/D converter.
Adding the capacitor effectively lowers the actual impedance that the ADC "sees". This is especially helpful if the ADC is setup with a very low effective impedance, like it originally was when the Spark Core first shipped.
Eh, somewhere in there is says it's low... I don't think it gives you a number per say. Ah, it's on the first page... just a little blurb that it's low. No concrete numbers. Basically it's up to you to calculate the impedance based on what you hook up to it's output.
Right, but that's a pretty long sample time... and now the maximum sample rate is 14.5 cycles, so 239.5 is achievable.
All that said, I have this unsettled feeling about it all 
I'd like to give you some more concrete info, but this is all I can offer currently.