Low ADC Readings

Not with Dual Slow Interleaved Mode... max is about 19k ohms because the max Ts that can be used is 13.5 :frowning: And I think the default in the core-firmware when set to 7.5cycles is 6.4k ohms. Which could explain why my master readings are so low. So if the purpose of converting the ADC to Dual Slow Interleaved Mode was to increase the input impedance, the goal was not achieved.

Check out my ramblings here...

More info:
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00050879.pdf

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/CD00211314.pdf

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/CD00258017.pdf

Somehow before I figured out that we were using a 12MHz clock for the ADC which slightly increase these numbers.

https://community.particle.io/uploads/particle/136/cbd022233addf534.png

Anyway you slice it, MAX Rain is 50k ohms:

However, I'd rather be closer to that, than 6.4k ohms.

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