New Gen3 Carrier for OneWire sensors

boron
argon
xenon
Tags: #<Tag:0x00007fe222b60e70> #<Tag:0x00007fe222b60a60> #<Tag:0x00007fe222b60880>

#1

I’m designing a new carrier PCB for Boron, Argon, and Xenon and would appreciate any feedback. It’s largely based on the great design from @chipmc, and as such I’ll be releasing it under the Creative Commons license once complete.

Here are the main features of this design:

  • 4 separate OneWire busses, with three exposed externally for sensors
  • Each of the three external ports (3.5mm headphone jack) can also be used as dry contact inputs
  • External watchdog timer to reset the Boron LTE (or other Gen3 device)
  • ESD protection on external OneWire interfaces
  • 32KB FRAM for storage of keys and certificates
  • Internal (on-board) DS18B20Z+ sensor for controlling charging current
  • protection on power inputs
  • Ability for the device to power cycle itself
  • Pushbutton to toggle power on/off
  • USB and LiPo power
  • OLED 1.3" monochrome display connected to the SPI bus

I have not started the PCB design yet, but wanted to share my schematic for any input the community may have first. I welcome all comments and ideas. I’ll update the schematic based on input received here, and then post the PCB layout afterwards.

Thank you in advance for anyone who looks at this and provides comments!


#2

Hi @picsil,
on top of the comments you may receive here, maybe you can build upon the ones on this thread as well?

Please ignore my comment if you had looked at it already.
Good luck!
Gustavo.


#3

Thanks @gusgonnet, I used that post extensively as part of my design. I didn’t incorporate all elements of it, but those that I thought relevant, plus some changes of my own.


#4

Hey picsil…I’m new as you know. I’m not a schematic reviewer, but I do have a question. Is the purpose of having three external OneWire busses to support mega DS18B20s (many on each line), or is it to work around the issue that impacts multiple sensors on particle.io’s OneWire implementation (that we have discussed on the other thread)?


#5

Great spec - you may want to put the display on the I2C bus and not SPI because if you want to add ethernet to the design - DeviceOS, SPI and the ETH wing do not allow additional SPI devices to work


#6

I used multiple OneWire busses (e.g. single drop) to make the product a little easier to use and simplify setup. My customers simply plug in one sensor per jack, and in software they identify what type of sensor each jack has. In the case of OneWire, I also report the device serial number, so I can automatically fill in the device type.


#7

Thanks, @shanevanj. I actually started with an I2C display, but due to either a quirk in DeviceOS, or more likely the displays I’m using, if the display becomes disconnected or damaged in the field while on I2C, the Boron completely locks up and is unusable. I did not have that problem in testing with SPI. I don’t foresee adding Ethernet since my product will typically be installed in remote areas.


#8

@picsil, OneWire is not ideally run on Gen3 devices ( e.g. see here). You may want to use a DS2482-100 (single channel) or -800 (8 channel) I2C-to-1Wire bridge chip. @rickkas7 has a great library for it and it will remove the “interfering” elements of the bit-banged OneWire library.


#9

Hi @picsil, nice to see more carriers developed. What is the criteria for picking the rating for F1? 1.5A seems high. I would expect it be like the other fuses.
Is Vin, mentioned in text, the left side of F1?
Would you publish the schematic in white background? I have a hard time reading it.
Pesc


#10

@Pescatore I got the fuse ratings from the original design by @chipmc. Looking at it further, Chip’s application is much different than mine and you’re probably correct that I should lower the rating of F1.


#11

I’ve made a few changes and laid out the PCB. I switched out the JST VUSB connector for Micro USB, and mounted the 3.5mm jacks and power button directly to the PCB instead of breaking them out with headers.

Unless someone finds glaring errors with this, I’ll send it off to JLCPCB next week. @chipmc, any advice on prepping to send out to a board house would be welcome! This is my first attempt. Thanks again for the great design this was based on.

EAGLE files: https://github.com/picsil/picsil-gen3-carrier



#12

First of all, I think you have done a great job here. Getting boards made and, eventually perhaps, getting boards assembled is a great learning experience.

Some comments that reflect some of the things I have learned over time:

  • I noticed you put a number of Vias but I would put some extras around the ground pin of the LiPo connector and Electron.
  • Careful about creating sharp angles when you connect two traces such as Vcc under U1, sharp angles can trap etching material - this is called an acid trap. Try to join traces at 90 degrees or more.
  • Use as wide a trace as you can - especially for Vcc. Wider traces carry current with less loss and ohmic heating.
  • Stick with a standard “grid” - if you can use mils (not inches) and the EAGLE default. This will make aligning parts and routing traces easier.
  • Run a design rule check specific to your board house’s specs and shoot for zero errors. If there are clearance or dimension errors, see if you can resolve with a different footprint
  • I noticed you are using D7 for DW2 - know that this is a special pin as it is tied to the blue LED on the Boron. I generally don’t use this for IO as that blue LED is quite useful
  • The footprint you are using for 0805 capacitors seems to put a small space between the pads under the capacitor (see C1). As, I assume, you will be hand soldering these, it feels like this could lead to a hidden short. Take a look at the Adafruit or Sparkfun cap footprint.

Please consider these comments but feel free to ignore as you wish as I am still learning myself.

Good luck and please share your progress.

Chip


#13

Thanks, @chipmc! I appreciate the comments. I’ve added some additional vias around the LiPo GND and Boron GND. I’m considering the rest of your comments and thinking of how to integrate them.

I will be placing most parts with a pick and place machine (CharmHigh CHMT48VB) so I don’t think I should be too concerned with the caps (but please correct me if I am wrong on that).

I calculated the trace widths based on expected current, and I’m using 20 mil traces for VUSB and LI+. The other traces I believe should carry the required current, and are well above the minimum at 8 mils. Should I increase these further?

I ran the standard EAGLE DRC and do come up with clearance and dimension errors. They’re around the USB connector J6 (too close to edge) and J1-J3 through hole pins at the top being too close together. I’m not sure if this is a problem or not. I want the USB connector to hang off the edge a little bit, and the J1-J3 footprints came from Mouser. The offending pins seem to be for mounting only. Again, not sure if this is a problem or not.

The DRC didn’t come up with any other warnings or errors. Not sure how to find one specific to JLCPCB though.

I am considering moving OW2 away from D7 as you suggested. I may want to use the user LED in the future, and I have a spare pin. I’ll most likely do this.

Can you elaborate on your comment about the grid size? I did change it in order to move the USB connector a little closer to the board edge. I don’t know if that was a good move or not. My intention is to have the micro USB connector firmly soldered in place, but leave some overhang for the connector to pass through the wall of the enclosure (2mm thick).

EDIT: Also, I’m not sure I completely understand your comment about acid traps. I was trying where possible to avoid 90 degree angles, ,but further reading suggests this is not necessary for low frequency circuits like this one. Would it be better to use 90 degree traces rather than having some at less than 90 degrees as you pointed out?


#14

@picsil,

Thanks for taking a look at my comments. I hope they are useful. You had asked for me to clarify a bit on my comments. Here you go:

  1. EAGLE grid size. EAGLE has a default grid and, if possible, you should try to stick with it - at lease for boards like we are doing here. I have uploaded what the default is and what yours is currently set to. Parts and traces will “click to grid” and having coarse grid makes it easier to align components and get straight and even traces. You can always make the grid more fine at the very end when you want to fine tune the positioning of a component.


Original Settings


EAGLE defaults

  1. See below where there are some fairly sharp angles in the way that two traces come together. These acute angles could trap the etching compound and cause the trace width to be less than what you intend. Especially since this is a VCC line, it may be worth fixing (see second photo for one approach).


Acute angles

Without acute angles

Note: there is some debate on whether this is still an issue for modern board manufacture. I read about this a few years ago and have been making these changes ever since. If someone has newer / better information on “acid traps”, I am all ears.

Also, this is just for where two traces come together. You should still avoid 90 degree angles, especially in the signal path as it can cause reflection.

One more thing, and I am not trying to start a board house religious war here, but I have used OSHPark over the years and have been very impressed by their boards, their service and for the time they have taken to explain issues to me when a board did not turn out as I expected. There was a Redit post on when JLCPCB is so much less expensive and the founder Laen responded with a very detailed set of reasons here. I thought you might want to see but, again, I am only providing information and relating my personal experience - you make the decision that is best for you.

Thanks,

Chip


#15

Thanks for the help, Chip! I’m headed out of town for a few days but will make a few tweaks when I get back. I’ll definitely check out OSHPark too. What is their typical turnaround time for your boards?


#16

@picsil, cool, glad you found it useful.

OSHPark has two speeds - normal 8-12 days and swift in 4-5 days for a premium price.


#17

I just placed my PCB order. Since this is my first ever PCB, I expect to go through at least a couple of revisions and turnaround time is important. I have a soft deadline of September to get my version 2 prototypes out in the field. I looked heavily at OSHPark but in the end decided to go with JLCPCB due to price and lead time. While I’m waiting for the boards to arrive I’ll be ordering reels of parts and figuring out how to use the pick and place machine.

I appreciate all the help I’ve gotten here. I incorporated several changes suggested in this thread, and the github repo has my latest design. I will update this thread once I receive the boards and get them assembled. I’m sure I will have more questions soon!


#18

@picsil,

Congratulations on your first PCB order! Good luck and keep us all posted on your progress.

Chip


#19

I placed the parts order today and should have the components within the week. Boards will follow soon after. I’m crossing my fingers that this will work, but I’m expecting to have to do at least a Revision B if not C before I get it right. @chipmc seeing the iterations you went through helped tremendously in designing this. I hope I gave the proper attribution on it since it was based on your design. I haven’t released anything under the CC license before, so please let me know if I should change anything in that regard.


#20

@picsil,

The fact that you are doing something useful with this design is all the attribution needed. Not too long ago, I put in my first PCB order and I benefitted from a number of good folks help and advice.

Chip