I use Photon and Particle Build, the web based IDE.
How many digital pins can I attach to an interrupt? Each having its own interrupt attachment. Is it really FIVE? (I have 6 sensors.) Another forum post about Core says it’s only five.
Documentation says that once you are in an ISR, no other interrupts will occur. Sounds good. How does the “system” (the combination of CPU and firmware we know and love as the “Photon”) KNOW when I exit my ISR and it can resume allowing interrupts?
Does the hardware keep track of when an interrupt occurs and “watches” for the return from the ISR to resume allowing interrupts?
Must the ISR code explicitly issue some directive like “resume_allowing_interrupts_after_I_return”?
- Documentation says there is a priority to the interrupts. To me, that means if a low level interrupt (one might say a “less important or less critical” interrupt) ISR is running, then a higher level interrupt (like DMA according to the documentation) can interrupt the lower level one. But that seems to conflict with point 2 above: Once IN an ISR, no other interrupts can occur.
Where is reality?
On some computers you have a priority of interrupts. But at each level of interrupt, you can have multiple things causing an interrupt. (Sorry, this is not explaining very well.) Does Photon have anything like this?
Can someone point me to deeper documentation on this whole subject? I understand that the folks at Particle are trying to provide a base set of functionality which works great for most users. (And it looks like they are succeeding.) But I see lots of posts talking about, for example, low level programming well under any base set of functionality. How does one learn about this deeper functionality?