The docs state that all Photon pins except D0 can be used for interrupts. But has anyone tested D5 (or other pins not allowed on the Core)?? Compiling from cmdline (particle flash XXX) does not yield a program that responds to D5, although D4 works. I wonder if illegal parameter code for the Core is still in place? Or is there a way to make sure you compile for Photon and not Core?
Woot! That’s great info, thanks a million for the pointer; will use that method from now on.
Unfortunately, after updating and doing a photon compile followed by flash, I’m still showing no response to interrupt transitions on D5 or D6. This would be expected for Core but had hoped Photon was different.
Any additional suggestions?
@kennethlimcp, it seems like that is the problem! @satishgn, would it not be possible to cascade shared interrupts by testing each respective interrupt condition? Is this a conversation I should have with @mdma?
If there are flags that are set to indicate the interrupt trigger that would be a perfect solution. I’ve not found any such flags so far, but I’m far from a STM32 guru. (Although searching brings me to threads like this one, which claim it’s not possible to service two different GPIOs on the same EXTI line because the internal N-to-1 demultiplexer.)
For the issue with Mode/D0/A5, it may be possible to rework the way the system handles the mode button to free up D0/A5 interrupts.
I have the same issue. I were running interrupt on few Photon from D0 to D4, D0 is the only one does not receipt anything. Glad that I only need to use 4 pins, so I use D4 instead of D0. I would love to see if there is any solution for this in the future.