@BDub. I don't see any issues dating 27 days back on this subject. But if this counts as cross-posting (here and GitHub issues), by all means chew me out 
Basically, after reading through some of the STM32F103 reference manual, it appears that the problem is entirely caused by the exclusive use of dual-ADC slow interleaved mode in analogRead. With that mode, the maximum permissible sample time is 14 ADCCLKs—explaining why selecting 239 ADCCLK sample time doesn't quite work. With both ADC1 and ADC2 sampling, you have a lower input impedance, not a higher one.
I'm experimenting with changing the ADC clock scaler from 6 to 8 (= from 12MHz to 9MHz), and completely removing all dual slow interleaved mode code. (That rhymes...) Basically, as I understand it, if you have two ADCs alternating on the same input line, you've halved your input impedance. AFAIK the only purpose for interleaved mode on the STM32 is for faster sample rates, not higher input impedance. Will update this thread based on my findings.