@BDub, @satishgn, both of your names are in the code file, so I have permission to pester you! Just for good measure, @bko, @ScruffR, @kennethlimcp…the solution to the ADC problem is here!
I totally disabled the slow-interleaved ADC mode in a month-old LATEST build, modifying \core\adc_hal.c:
- HAL_ADC_Read: Commented out all references to ADC2 in (
ADC_RegularChannelConfig, ADC_ExternalTrigConvCmd
)
- HAL_ADC_Read: some optimizations to the sum/divide averaging routine, also removing the
ADC_DualConvertedValues[i] >> 16
and the *2 from the final division
- HAL_ADC_DMA_Init: Changed ADCLK to
RCC_ADCCLKConfig(RCC_PCLK2_Div8);
(instead of Div6. Don’t think that this is important)
- HAL_ADC_DMA_Init: Disabled ADC2 clock
- HAL_ADC_DMA_Init: Set ADC1 Mode to independent (
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
)
- HAL_ADC_DMA_Init: As it’s no longer interleaved, I had to also enable the continuous conversion mode on ADC1
- HAL_ADC_DMA_Init: Commented out all ADC2 initialization code.
With the above changes and ADC_SampleTime_239Cycles5, I get the following readings:
- A4 to 3V3* -> 4095
- A4 to 3V3* with 330K (no capacitor) -> 4065 (pretty high impedance if you ask me)
- A4 to 3V3* with a 330K resistor and 0.1µF capacitor -> 4093
- A0 to 3V3* -> 4084
Experimenting with ADC_SampleTime_1Cycles5:
- A4 to 3V3* -> 4094
- A4 to 3V3* with 330K (no capacitor) -> 2700 (looks low-impedance, alright!)
- A4 to 3V3* with a 330K resistor and 0.1µF capacitor -> 4092
- A0 to 3V3* -> 4083
Just for proof-of-principle, I replaced “adc_hal.c” with the latest LATEST “adc_hal.c” (making a backup of my changes, of course!) With my system code completely untouched (@ADC_SampleTime_239Cycles5) I get the following:
- A4 to 3V3* -> 3890 counts
- A4 to 3V3* with 330K (no capacitor) -> 3714
- A4 to 3V3* with a 330K resistor and 0.1µF capacitor -> 3888
- A0 to 3V3* -> alternating 4084 and 3879
And with ADC_SampleTime_1Cycles5…
- A4 to 3V3* -> 4094
- A4 to 3V3* with 330K (no capacitor) -> 2642 (ditto)
- A4 to 3V3* with a 330K resistor and 0.1µF capacitor -> 3888
- A0 to 3V3* -> 4083
I haven’t dug through the firmware to see if the Core’s A0 translates to PA0 on the STM32, but there is a documented nonfixable problem in the STM32F103 errata regarding a “glitch” on A0, as follows:
FWIW, I’m checking A0, A1, A3, A4, and when not connected to anything with the unmodified firmware they read as follows:
- with ADC_SampleTime_239Cycles5: 4, 1823, 1986, 2034
- with ADC_SampleTime_1Cycles5: 883, 2069, 2095, 2145
I don’t recall hitting A0 with a sledgehammer (and this is a different Core than I was using in the opening post, too!)
I hereby submit that the dual slow-interleaved mode should be completely removed from the official firmware. It appears to be the source of the problem documented in the opening post.
Oh, and by the way, removing all that code? It results in a slightly smaller firmware file.