I am curious about the low power options using a P1 module. If I designed a custom battery powered carrier board,how would it go?..
Say I thought to myself… “Hmmm. I only want to switch it on 1% of the time. I’ll just use a 3V CR2032 and a boost regulator. That’ll be fine with 320mAh capacity. It’ll last for months!” That would of course make me an idiot. Because at 100 mA, a CR2032 only realises about <1% of it’s rated capacity. So, my nice 320mAh battery is now a 3mAh battery. And probably wouldn’t last long enough to get through the claiming process. So let’s not do that.
So then I think to myself. Fine I’m going to use alkaline batteries. Pity they are so big! How should use the sleep modes? So, it boils down to what modes are available. And how do you wake up from each? Obviously, the stock sleep mode can wake up with an interrupt : handy. But the current is very high either 30mA or 2mA depending on which document I believe, both of which are way too high. Deep sleep uses a predetermined timer to govern wake up. This gives 80uA current, which is better. I see that there is the option to add a wakeup pin to the deep sleep function. Still at 80 uA? No way of knowing without testing it, but based on how every other uP I’ve ever used, I would assume yes. None the less, it would be great if this information was available to avoid wasting time. And for what it’s worth, 80uA is really high for deep sleep. I genuinely want to do nothing but wait for an interrupt during this time.
It’s here that I stumble upon something really odd in the photon documentation. It states that the deep sleep power consumption is 3.2uA for the core, but to consult the Photon data sheet for that. And it’s 80 uA. This seems off. So the core has better low power performance than the photon, or P0, P1 for that matter? That doesn’t make sense to me. Unless the 3.2 uA was a typo.
Back to the P1. There are four 3V3 inputs, 2 for the Wifi (VDDIO_3V3_WL&VBAT_WL), one for the uP (VDD_3V3) and one for data retention purposes (VBAT_MICRO). I’ve rummaged around and found the “datasheet” for the P0 module, as supplied by the original manufacturer. It is light on detail. But it would appear, based on the very superficial block diagram, that you could just completely power down the broadcom chip by grounding the 2 WL supplies, omit the optional VBAT_MICRO, and then if run the uP in deep sleep mode. Which I imagine must correspond to ‘standby’ for the STM32F205RGY. And having a quick look through that datasheet, there’s actually no reason why you couldn’t achieve < 5 uA, so maybe the spec for the core was real?!. I’ll have to suck it and see on this one unless anyone has definitive conclusions on the matter. It would have been quicker to get the soldering iron out, except for the fact that I only have a couple of devices, and it takes weeks to get more to my location.
As an aside: It may be cracking a nut with a hammer (my speciality), but what would happen if I completely removed the supply to the P1 module, and restored it when I needed it again. Is there anything wrong with this approach, other than being ugly as hell. The P1 will remember the wifi setup information etc, won’t it? This could all be achieved pretty easily in hardware.