FPGA Spark Shield

I’m a new Spark user and thought that it would be a perfect platform to do some projects around the house. However I need to add some programmable logic to it and am thinking of designing a shield that contains an FPGA. There are also a couple of consulting projects I’m working on where a wirelessly connected FPGA with some custom logic would be very useful. My cursory search didn’t turn up anything like this so I’ve begun planning to design one. I’ve done a lot of work with FPGAs and other programmable logic in a previous job. Since all this experience was with Altera FPGAs I am leaning toward a small Altera FPGA. The four lowest members Cyclone IV family come in a pin-compatible 144-pin QFP that would offer a range of logic element counts from 6K to 22K. The closest Xilinx offering is the Spartan 6 family that offers a choice of 4K or 9K logic elements in a 144-pin QFP. I’m curious if there is any interest in such a shield board and, if so, if there are any thoughts on the choice between Altera and Xilinx and size of the FPGA to use.


I’ve heard rumors of an FPGA shield in the works. Maybe @zach or @zachary can give more details.

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This is that shield! Charles is the man behind the idea.

Just wanted to throw out my two cents on the shield, which is that I think it’ll be awesome. I know very little about FPGAs, but the idea of reprogrammable hardware that can be redesigned wirelessly kind of blows my mind. Would be really curious to hear if there are people in our community with FPGA experience, and if they’d be interested in such a product.


Well in that case, I’ve been very curious about FPGAs for a long time, but didn’t know where to start. If this is something that could also be used as a learning tool for noobs, I’ll tag a long for the ride. :smile:

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That’s an interesting point. My focus has been on designing something that would be useful in a few projects I have in mind. With the tool set that I use, there are two ways to program the logic in the FPGA. One is a hierarchical schematic capture system for old-time hardware designers who like this way of designing. The other is to use a hardware design language most likely Verilog. The tool set includes a full simulation capability so designing logic in an FPGA is much like designing an ASIC.

In my current thinking the shield would have just the FPGA and support circuitry (power supplies, clock generation, and non-volatile program storage) with headers to attach external logic. To make it useful to someone who wants to learn without building a daughter board, it would be possible to include something to show things were working. LEDs would be a trivial step in that direction, but there might be other simple circuits that could be added learning how to use them. I’m open to suggestions along those lines.


To make the FPGA reprogrammable over the air (OTA), you’d probably need to make the core into a JTAG programmer, but that sketch could be transient and you could then load a sketch that actually talked to the resulting FPGA personality and acted as the interface to the cloud.

Could be a very powerful idea indeed. What’s the prior art in the Arduino world ?

Please pick an FPGA with simple power supply requirements, complicating the design with power rail sequencing would be a bit of a headache.


ou might want to look [here ][1] for ideas. The Mojo was another Kickstarter project that I backed last year. Howver my taste in FPGAs these days run in the Xilinx Z7020 and Kintex/Artix series and I found the Mojo a little underwhelming so haven’t used in a while. However his approach is probably about right for the hobbyist community.

Back two or three years ago when the Maple was thriving, Leaflabs was considering producing “Oak” which was a STM micro-controller and FPGA combined. It never came to anything (to my knowledge). I did post some comments on FPGAs to their forum at the time which I have copied below as they may be germane. I was a nebie FPGAer and much had to do will my learning experience and the sophistication of the took kit (Web Pack) and VHDL/Verilog.

 This topic thread has been quiet for a while, so I thought I would try to liven it up.

I got my first maple (I now have 4 of them) a few weeks ago and when I read that LeafLabs plans a Cortex M3 and Xilinx Spartan 3E FPGA on the same board (Oak) I got very excited about the prospects. To speed the learning curve and to get the old juices flowing about possibilities, I now have a Nexys 2 FPGA development board from Digilent (yah, I know the ChipKit people) with a Spartan 3E 500K gate FPGA in a 320 pin package.

I have just started learning and playing with the development board using Xilinx's free WebPack toolkit and I think my experiences as I progress with this endeavor may be interesting and useful for thread readers.

First off, a bit about myself. I am a semi-retired systems engineer who lives in a cabin on a mountain in WV (Almost Heaven West Virginia). Not the greatest place for high speed internet access; I'm about 500 meters beyond the max length of a DSL connection, and that combined with an ISP service oversold and underpowered bandwidth wise from the local communications company, leads to iffy and unreliable DSL connection. I have been in the IT industry for more years than I care to remember (> 40) and still work part-time as a security consultant to one of the nation's largest defense contractors.

I started as a hardware field engineer on mainframes back in the late 1960s. Its amazing that the maple can probably outperform that original system (a Univac 494) which at the time ran the real-time reservation system for Australia's domestic airline, maybe many times over. If I still had the logic diagrams (and the patience), I could probably rebuilt that mainframe into my FPGA development board today with most of the capacity of the FPGA to spare. The capability and potential of what we have today is just incredible. Since those times I moved into software development, operating systems design, and eventually consulting.

Moving onto WebPack. Some of the earlier comments in this thread regarding vendor tool chains; the 3.8 gigabyte download and my internet connection; and MS Windows only install had me a little skeptical and nervous. I used a Mac development environment. I run Windows 7 in a Parallels VM for windows stuff and I realize there are some useful tools out there that will only run in windows. Anyway, the WebPack download and install from Xilinx was smooth and painless. I downloaded their latest version (at the time) 13.1. They have a download manager that handled without trouble the restarts caused by two lost connections during 3 hour download. The install was easy and smooth, and registering and licensing of WebPack (free perpetual license) made simple via interactions with the Xilinx License Manager website.

WebPack is a complex package of many different toolsets, but Xilinx has done a good job of knitting them all together using the ISE Navigator. Given the high version number, I don't imagine this has been a very easy or fast evolutionary process, but what they have today is pretty together and cohesive from a new user perspective. For the best perspective on the FPGA development process I recommend downloading the latest version of theSpartan3E_UserGuide from Xilinx. Starting at Chapter 13 "Using ISE Design Tools" is an amazing well-written (no engineer speak) and coherent walkthrough of the design and implementation process and how to accomplish it using Xilinx ISE tools, including WebPack.

I think that will do it for now; as I progress further, I will add updates. The feeling of accomplishment from installing something as simple as a 8 input XOR circuit, and watching the Led turn on and off correctly as I set/reset switches on the Dev board is incredible. Off now to learn more about VHDL :-)


Hey pra, thanks for posting. I don't go back quite as far as you but I do remember working with 300MB disk drives the size of washing machines and thinking 8" floppies were pretty spiffy, to use the technical term.

Please do post your FPGA progress and your thoughts on Oak here, I'm interested in it too but I don't see a huge amount of discussion of the device lately. Any more tips like these on what resources you find useful for learning FPGA development are well appreciated, and hopefully I'll find some time to follow along at some point. Maple looks great, but it's a little like an Arduino on steroids. Oak is a different class of animal entirely. Maybe even a different phylum.


a little FPGA learning progress to report. I started with some basic tutorials, mainly from Digilent's website, to create a basic gate, synthesize it, map and route it into the chip, and create the the bit file for downloading. Next was learn Adept, Digilent's free tool for downloading bit files into the device on the dev board. Pretty straight forward, but you learn pretty quickly where and how to set CCLK to J-TAG CLK in WebPack.

There are lots of WebPack tutorials out there, some from Digilent, some from Xilinx, and some from Universities - all are free, and all reference a WebPack version from the past. Consequently, you can't just follow along; you have to figure out how to accomplish the same goal using version 13.1. Not a bad thing, I guess, as you actually need to understand the process and the step you are trying to take to get it to work. The biggest differences with 13.1 and previous seem to be Navigator tabs and other layouts, Workbench test creation, the simulator, and creating User Configuration Files (ucf). 13.1 uses ISIM lite for the simulator, which is different from the past, probably different to the full version in the full ISE, and definitely different to the various versions used in tutorials. It's quite capable, but you are definitely on your own learning how to use it. Workbench tests seem dramatically different from the past where the wizard appeared to give you a waveform editor to create your test. 13.1 gives you a VHDL module pre-filled with essential stuff, but you have to code your own test process. Once you get it syntax correct, you can use it to open your ISim module and then you have your waveform. Want to change something, back to VHDL.

To run the design process, you have to have a user constraints file to map your signals to FGPA I/O pins. WebPack 13.1 uses the Plan Ahead tool to do this graphically, but I have found this not to be overly useful. For myself, and I suspect the majority of the Leaflabs community, we are not designing a new system using a FPGA; we are using an FPGA that is part of an existing system, such as Oak or a FPGA dev board. Consequently, many (all??) of the FGPA I/O pins are already assigned to other components on the board, such as peripheral connectors etc. My Nexys 2 board for instance, provides connections to 8 switches, 8 leds, 4 push buttons, a 4 digit/7 segment display, a VGA port, a RS-232 Port, a PS2 port, the USB port, 4 x 12pin peripheral connectors, and a 40 pin expander board connector. So the ucf I use is the one I downloaded from Digilent for the Nexys 2, and I copy that into all my WebPack projects. I edited all the NET lines to comments so that I can enable only the connections I am using in this project...and it's way easier to deal with using a text rather than a graphics editor.

Which brings up an interesting issue, and maybe one reason Oak seems slow in appearing. Other than the Nexys 2 ucf, I don't have to include anything else; the FPGA belongs to me and I can make use of what it and Digilent provides as board hardware any way I choose. Leaflabs is producing a system in which the FPGA is a component. As part of the Oak system, I'm sure Leaflabs has specific (what do you call this stuff, files, code ...) files that are loaded in the FPGA that help make the overall system work. Anything new loaded into the FPGA will need to incorporate the LeafLab suite, and be compatible with same. Oak is orientated towards the hobbyist community, not EEs, so this integration process needs to be foolproof yet easy to use, otherwise LeafLabs will spend all their time in support and handholding, not creating the wonderful new toys we all wanted from them yesterday. Yet, this is not a simple process, synthesis and design mapping, routing and performance tuning is a complex area totally dependent on the specific flavor of FPGA being used; something only the FPGA manufacturer is able to do well. So, I imagine LeafLab's challenge is how to come up with an easy-to-use yet foolproof tool chain that automatically includes what LeafLab needs into in the build so that the system is not compromised, yet still use Xilinx XPS and other design suite tools to make sure the FPGA is used efficiently.

When you buy a dev board from Digilent you have the option to bundle it with a "how to" text book and save a few bucks on the individual purchase. The book I chose was "Digital Design Using Digilent FPGA Boards", published by LBE Books. This is all about VHDL. You can certainly use the WebPack schematic editor and the library of packaged logic components to create meaningful solutions, but you can only tap a small portion of the FPGA capability that way. So, if you are serious, VHDL or Verilog and boolean algebra are in your future. This book had me knee deep in boolean algebra and K charts by Chapter 2; I tried skipping over it all, even though I once knew all this stuff, because now it just makes my head hurt; but no way, there is no alternative to knowing and understanding this topic if you are going to design efficient logic circuits.

I have worked my way through into Chapter 5 where I just created a circuit to display the hex value of the switches 0-3 on the 7 segment display. When I first ran it, the display looked like chinese. I even did the K-Chart from truth table exercise, so I was sure the logic was right, and the simulator said that I was correct. I was selecting the right segments for each character, but not according to the board. Then I looked at how Digilent defined the 7 segments in the ucf, and yes, they were in the reverse array order to VHDL's "6 downto 0" vector assignment. Some ucf editing and Bob's your uncle :-).

Now for a Clock Divider project to add to the seven segment display so I can display a 16 bit hex value and accomplish something I hope results in my first "keeper" project.


Taking a break from FPGA for a few days to let my poor brain settle a bit. I've become fairly fluent with WebPack and its features. It's definitely a good product and straightforward to use, but there is so much to learn about the FPGA process. I have completed working my way through the "Digital Design" book and implemented all of the examples I cared to. The most sophisticated was getting the 4 digit 7 Segment display on the Nexys 2 to scroll out my cell phone number.

I have become moderately competent in VHDL and have created a number of designs of my own in VHDL from scratch. Given all I have had to learn (and must still learn) about FPGA design and usage, learning VHDL was a minor undertaking, one that I feel absolutely necessary if you intend to make use of the enormous capability of a FPGA. You can barely scratch the surface with the schematic approach. I did a couple Xilinx video tutorials on making efficient use of the Spartan 3 and found them helpful and logical. Armed with this knowledge, its been interesting to look at how the Synthesizer generates LUTs, Roms etc. based on my VHDL statements. For example, the tutorials suggest that "case" statements are the most efficient form of coding certain logic, and the synthesizer appears to turn these statements into a Rom built from block ram, maintaining the same pin to pin speeds, but using much fewer number of LUTs and slices.

I have experimented with the Block Ram capabilities of the FPGA. Two options were available. BRams of various sizes are available via the Schematic Editor and the symbol library. These have no documentation and its difficult to tell exactly what all the signals are etc. without documentation. BRam can also be generated via the Core Generator. Here there is extensive documentation in the form of a comprehensive datasheet, and complete options to configure the device to what you need. It would appear that the Core Generator has superseded much of the symbol library, except for basic logic components. I tested my generated BRam with ISim by writing each cell's address to each cell's data storage, and then reading it back out. The test bench VHDL to do this was straightforward and it all worked beautifully. I recommend you bite the VHDL (or Verilog) bullet, because that is the only way to take advantage of the wealth of stuff Xilinx and partners make available. As mentioned before in this thread, the major challenge is understanding that this is not a sequential execution process like that with a normal language; everything happens instantaneously, simultaneously and continually.

I have built a design that I have running with the ISim simulator and will test in the real world via my LCD display device (see different post). It is a 15 channel SPI interface, utilizing only MOSI, MISO, SCLK and four I/O pins on the microprocessor to select the 1-15 independent devices via Chip Select. I know I can basically build this with a 74HC154, but with the FPGA, I have niceties such as keeping all devices off the microprocessor I/O lines via tristate buffers until they have CS active etc. I have also made a 7 SPI device version, but the saving in microprocessor pins here is not as dramatic.

  [1]: http://embeddedmicro.com
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Somehow I screwed up the link to embedded micro and i think its important to take a look, so here it is again embeddedmicro.com

FPGAs (and formerly ASICs) are my area of expertise, so I am very interested in this as well. I think the Spark core could make a good “transient” JTAG programmer for the over-the-air updates, and then the FPGA would make a good universal peripheral for the core.

Both Altera and Xilinx are good, but I am more plugged into the Xilinx world right now. Which ever you choose, folks will need to access the toolchain (ISE/Vivado or Quartus), no matter which design methodology they use to design for it. These are tools are for sale, but often given away to customers.

Existing solutions include the Mojo mentioned before (which interestingly is export controlled):

There have been lots of reprogrammable FPGA solutions with Ethernet, PCI, etc, but I can’t think of one with just WiFi.

There is also this project:


This might be described as Arduino multicore, which is interesting.


Ive never looked at fpga’s or asics before so i dont have much of an understanding of what they do. But for their price (£20) for the 155pin, it looks like something that could be interesting to learn and hopefully a decent price. This may be the excuse i need to buy another core :slight_smile: