Determining Highest Frequency Generated by P1

I am planning on getting a design tested for FCC Part 15 Class B Unintentional Radiator. The testing house is asking what is the maximum frequency generated by the device is.

Does anyone know how to determine this for the P1?

There is a bit of a price jump in testing if the frequency is greater than 108MHz. Below is the statement of work.

Hi @wesner0019 the main system clock of the STM32F205 on-board the P1 is set to 120MHz and Wi-Fi signals are well above 108MHz, but since the P1 is certified by the FCC I would think frequencies generated by the P1 module are exempt. Perhaps they disable the radio during testing?

More info here:

Pinging @will on this as well just in case I’m way off about this.

@BDub, they would only be looking for signals generated for the additional PCB design I’m thinking. I have both SPI and I2C on my board but not sure how to determine the highest frequency generated by the board. I’m guessing that the SPI lines would generate the highest frequency.

If you are using a SMPS to power the P1, that’s probably going to be the highest. Usually these are around 1 to 1.5Mhz. SPI clock frequency can be set in firmware, but is no higher than 30MHz.

SPI system clock is 60MHz and SPI1 is 30MHz on the P1, but since the minimum clock divider is 2, this makes SPI SCK (clock) 30MHz and 15Mhz respectively.

I am using an LDO for the power supply, so no high frequencies from that. I think I read somewhere that even though the system clock for SPI is a maximum of 30MHz, the rise and fall times of the signals can generate higher frequencies?

I maybe far off remembering, just wanted to through that out.

Yes that’s true. You can create high frequency ringing at the leading and falling edges of any square wave. 100kHz square waves can easy generate troublesome 40MHz EMI. Usually this is more of an issue with power circuitry though. Is your design going through FCC now or are you just putting together quotes?

I am just putting together quotes for testing soon.

Generally, these questions on an unintentional radiator test are looking at frequencies external to the chips in question; internal PLL and bus frequencies (eg APB, AHB) would not be counted, but any crystal in the module would be.

The Broadcom chip generally uses a 26MHz xtal, so that’d be the highest number you’d quote unless you were running at SPI at 30MHz. The question they are asking determines how far up the spectrum they will look for harmonics.

As @Bdub says, edges cause noise - if you’ve ever taken an FFT of a square wave, you’ll see the harmonics go on forever. You should use the minimum drive strength on any external buses that you can get away with (note that unless you have a FET probe on your scope, you’re going to affect edge rate significantly by just probing a pin). The STM32 has programmable drive strength on pretty much everything.

General hints on passing unintentional radiator tests, from someone who has been there and done that quite a few times! :slight_smile:

  • Use a 4+ layer board. A solid ground plane (clean current return paths) is the biggest thing to give reduce radiation. Yes, stuff can pass with 2 layers, but it’s a tough thing to manage especially with wireless. Spend the money on the 4 layer board.

  • Bypass caps close to any digital power users. Minimize the loop area (imagine the current is coming from the cap, to the chip power pin, through the chip, into the ground plane and back to the cap - make that loop physically as small as possible). The smaller the package (think: CSP vs a QFP with bond wires) the smaller the area and the less noise issues you have.

  • Be careful with your power plane design, cutting it up (or, heaven forbid, the ground plane) is bad.

  • Analog ground planes should only be used if absolutely necessary. They are usually more trouble than they are worth - better floor planning generally gives better results. eg: no iPhone has ever had a split plane, even for the audio, and we got the audio noise floor down below -120dBV with the codec right by the processor.

  • Add source termination resistors if you are running (eg) fast SPI. Place these as close as possible to the driving end.

  • For any signal that leaves the board on a cable (be it a wire, a flex, a power input) place pads for filter components - a series pad (where you can stuff a ferrite bead if you’re unlucky, or a 0R resistor if you’re lucky) and a pad to ground (where you can stuff a small cap if required to shunt high freqs to ground). THIS IS REALLY IMPORTANT. If you can clean up your emissions by using pads and a sample kit when in the lab, you (a) get a pass whilst you’re there and (b) don’t have to spin your board and start all over again.

  • If USB is leaving your board, place a CM choke on the lines, with 0R bypass paths just in case you’re lucky.

  • If you’re using a switching PSU, copy the vendor’s layout recommendations EXACTLY, including via placement.

Good luck!


btw, NWEMC are a good firm, we’ve used them before. Clueful is good in an EMC lab, and not all of them are :smile: