Could the documentation be fixed please?
The firmware docs state that SPI speed for generation 2 devices is 60Mbit/s (and has been stating that for years) in a number of places but it is not correct. The STM32F205 manuals states that SPI uses APB1 or APB2 clocks not system clock to drive the SPIs (1-3) and both of those are subdivisions of system clock: APB1 at 30 MHz and APB2 at 60 MHz. This together with minimum divider for SPI set at 2 (as per STM32F205 reference) will give an absolute maximum SPI speed of 30Mbit/sec and SPI1 at 15 MBit/sec.
@AlexeyDanilchenko, you are correct. I believe the max SPI clock for “SPI” on the Photon and Electron is 30MHz while “SPI1” is further divided by two for a max clock of 15MHz. @rickkas7 can confirm.
Yes you are correct: APB2 is 60MHz (SPI is on this) and APB1 is 30MHz (SPI1 is on this). Amended my original post to specify that.
It does appear that Gen 2 devices (STM32F205) has a maximum SPI clock speed of 30 MHz for SPI and 15 MHz for SPI1, not 60 MHz and 30 MHz, because the smallest possible divisor is 2 (SPI_BaudRatePrescaler_2) not 1.
I created an internal ticket to fix this because it’s weird that this hasn’t been reported before and I want to make sure we’re not missing something before making the change, but the person I need to talk to is on vacation this week.
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