Unfortunately much of the work I did happened before the newest change which implements the Dual Slow Interleaved ADC mode, AND apparently a 10 sample average. This does change things quite a bit.
Also from what I remember this mode is not effective at higher sample rates than XX… and possibly forcing the sample rate to be higher than XX could be what’s causing the issue. Looks like your results do tend to show this. If you search for my previous replies about Dual Slow Interleaved mode you’ll see some of the calculations.
I would start first by removing the 10 sample average, this should be something the user has the choice to implement. Since this averaging exists now though, maybe roll it into a configurable User API. ( It sounds like this was added as a band-aid to give better results, but just one bad reading will corrupt the whole 10 reading average.
Then re-characterize the readings, taking one sample per second and logging them.
Also, tie your A4 to the 3V3* pin, and A5 through 22k to the 3V3* pin. This is the VDDA (adc reference) of the Core.
I wish I had more time to look at this right now but this is the best I can offer. If someone else can verify that this is truly a bug (or if you insist that it is @WebDust21) , I’ll add it to the firmware issues to be addressed in the near future. Thanks!!