Using a digital Output pin to control power to peripherals [solved]

I want to use a digital output pin to control power to peripherals on the circuit board the photon is situated on. The need is to reduce power consumption by the board whilst in low power/sleep mode.

What happens to the digital output pins when in sleep?

Should I use active LOW or active HIGH on the control pin so that when the photon is in sleep mode it can still have the peripheral power off?

@armor, how much current are you expecting to use? In deep sleep, all pins float while in regular sleep, pins maintain their states.

Often, an external MOSFET (eg. 2N7002) is used to control the high or low side of the power to peripherals. A pull-down to the MOSFET gate will keep the peripheral OFF, even when the controlling GPIO pin from the Photon is floating.

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@peekay123 The maximum measured current to the circuit board is 330mA. I have been looking at switching the +5V supply (high side). I was looking at a FDN304P which needs the input pulled low to turn on but realise that I need to be switching the GND bus (low side) with a pull-down rather than a pull up. Thanks

Hey, everybody!

I’m looking for some help in verifying if I’m doing this power control correctly using a FET.

I have a 4D Systems LCD display, and I want to use a FET to cut all power to the Display when I do not need it to be ON. The screen pulls to much power when put into a sleep state so using the FET to cut all power will prevent the constant power drain the various sleep modes have.

I picked out this FET since it handles the current the LCD requires.

Here is how I have the schematic laid out.

I’m assuming its best to cut the GND to the LCD to maybe prevent leakage current to GND via where the Photon/Electron connects it’s UART TX and RX ports to the RX & TX ports on the LCD display? Not sure about that though.

I’m not sure I have this correct, so I’m reaching out for help and feedback on this instead of guessing and having to fix it later :slight_smile:

The 1K pulldown is just a placeholder. What value is recommended for this?

@RWB, you selected a bipolar transistor, not a MOSFET. A properly selected MOSFET will have a low ON resistance producing very little voltage drop. The bipolar transistor will exhibit a voltage drop of between 0.4 to 1v depending on the bias current. You can use an N-MOSFET rated for 600ma or more drain-to-source current with a low gate ON voltage between 1.8 and 2.5v. You can use a 10K resistor (or even 47K) for the gate bias and you can probably get away with not using a current limiting resistor for the GPIO to the gate. Ground return can be a real pain and it depends on the device. You can configure the MOSFET for either high-side or low-side switching so experimenting may be a good idea. :wink:


@RWB, if you want to switch the high side (+5V supply to the display) this is a schematic excerpt from the design I am using to switch a 5V bus to all peripherals. This works if you want a definite BoM/schematic to use.:slight_smile:

In my case there is a voltage regulator for 3V3 and a mix of 5V and 3V3 peripherals which is why the high side was switched. I accept that switching the GND is better but there are also downsides WRT the ground plate being split. In this scheme the 5V is switched on when the photon pin is LOW. Clearly, in STARTUP() you would need to set the pinMode() and set it to LOW.


@armor Thank you for sharing this.

So Q3 allows the 5v to flow to 5Vsw when the gate is pulled low.

What exactly is Q4 doing? Looks like it’s cutting the Gate from GND.

Couldn’t you just use a Photon pin and pull down resistor to control Q3?

@RWB I would need to leave answering your question to those better qualified than me. I believe the issue Q4 solves is when the photon is in sleep and this arrangement avoids anything connected to the switched 5V supply from sourcing a current through the photon pin which is active low and hence would be high to turn off the MOSFET Q3. I hope that helps - you may need to take qualified advice :slight_smile:.

@RWB, though Q3 is switching 5v, it could be switching 12v just as easily. Q4 is there to isolate the GPIO from the (potentially too high) pull-up voltage at Q3’s gate (via R21). With 5v, you don’t absolutely need Q4 since the GPIO is 5v tolerant. However, Q4 provides extra and desirable isolation.

As @armor indicates, Q3 prevents the GPIO from sinking the current through R21 when the pin is LOW. However, at 5v, the current is only 50uA.

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One needs to be cautious about how to handle cutting the power to a device like this.
On a digital device / IC its typically not a good idea to cut the GND to it while the power line is still there. Weird leakage currents can then happen with the other pins that are still connected.
Just make sure for all the other IO pins going to the display you set them as inputs HI-Z state BEFORE you send the signal to the FET to cut the GND power.

Another option would be to use a non inverting buffer IC with an OE control line in-between your Photon and LCD. Pass all your signals though this so you can isolate your pins from the LCD when you want to power it down.

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Thanks for pointing this out.

I picked a new Mosfet, is it OK for logic level 2.5-4.5v control?

@seulater I decided to switch the 5v+ line feeding the LCD instead of trying to cut the GND to avoid ground differential issues.

Does this schematic layout look OK or am I missing something?

Is there uA of current being burnt/wasted when the FET gate is held LOW in this configuration?