I’m developing a PCB for a device that contains two ADS1115, 16-bit ADC’s which currently work beautifully on the Photon, and not so great on the Electron. I’ve used these ADC’s for years with the Photon’s and have never had an issue, but with the Electron, I pickup quite a bit of what I assume is EMI interference.
My question is: what can I do to reduce this interference on the PCB itself - is there anything other than including a full-blown faraday cage? Are there some things I can do on the firmware side as well?
Without seeing your PCB and a schematic, everyone will need to guess, but I would suggest you start by shutting off the radio during sampling.
Sorry about that…should have included this:
Let me know if the link isn’t accessible and I can try to change the permission. I’m sure there is plenty to be improved (welcome to any recommendations), but the noise is certainly the main issue right now on the ADS1115’s.
Suggestions off the cuff:
Add decoupling caps to electron. I see 0.1uF on the ADC, but consider this on the electron as well.
Consider using multiple values of decoupling caps in parallel to add to the range of frequencies that will be shunted to ground.
Look at your power return paths and consider the effects of loop inductance
Consider moving to a 4 layer board
Scope your PCB and try to determine the type of interference. Turn off the radio. Does the noise go down?
The PMIC switching noise is periodic and should should be distinguishable from RF induced noise.
Consider implementing a hardware or software filter. I’m not sure what your sampling rate is so I can’t offer more than that.
One major difference between the photon and electron is the PMIC, which has a different switcher than the photon. Look at those differences
I am assuming that your PCBs are identical between the designs with the exception for the added IO of the electron so you don’t have to consider PCB implementation changes.
OK, I had a few minutes to look at your PCB. I don’t know that this is necessarily the source of your problem, but I am seeing all kinds of vias in your signal lines that are there for reasons I don’t understand. So, one last suggestion would be to run your traces in the shortest direct route keeping in mind the total loop area that the signal will follow on its return path. This loop area will substantially affect whether or not you pick up interference from other sources. I’ve circled just a few of these via paths for which I don’t understand why they are there other than some type of software issue or that they were leftover from previous iterations.
@LabSpokane yea that’s my bad. The reason for those was to eliminate islands in the ground pour on that layer - I guess I’m not sure how to do that without moving to a 4-layer board.
I will definitely add some more decoupling caps and am currently experimenting with the cell module off to see how much that reduces the noise pickup. Sampling rate on the ADC’s is very low - the ADS1115 is pegged at something like 760 SPS, but I’m much lower.
I’ll also look into the PMIC to see if I can find anything there.
Do you have any good recommendations for resources on learning how to design PCB’s well? I’m not an EE, so I’m pretty much going off youtube and random online tutorials, though it seems like there is quite a bit of domain knowledge that is learned on the job. Anyways, thanks for the recommendations!
@hagandh, one thing you may want to consider is stitching your ground planes together. Altium has a good explanation:
Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net, to that net.
In RF designs, to help reduce crosstalk and electromagnetic interference in a route that is carrying an RF signal, a via shield can be added. A via shield, also known as a via fence or a picket fence, is created by placing one or more rows of vias alongside the signal’s route path.
You may want to do some reading on this and how to best apply it to your design.
Ground plane stitching is an excellent tip. I would definitely use that to protect your analog signals.
Thanks for those tips @peekay123 and @LabSpokane. I’m curious as to how ground-plane stitching is different than what I had done on other parts of the board - my intention was to stitch the bottom and top ground planes together with vias, but maybe I did it incorrectly. Is that what you’re referring to? I will certainly read up on it a bit more, and also learn a bit more about fencing. I have seen that on the Particle E-series breakout board and was wondering what the purpose was.
Is it better to fence off the analog input traces? Or the trace with the RF signal? In the latter case, how is the RF signal being transmitted on the Electron? I assumed is was taken care of by the Electron itself, and just the antenna would be of concern, but I (obviously) could be wrong…
@hagandh, you need to fence off any trace that can emit or receive RF signals! Another thing you may want to consider is RF beads as part of your decoupling. Another member recently posted a design that used them but I can’t remember which one! Google via stitching to understand the application and density of stiching vias for RF design.
RF is a tricky world. There are obvious things you can do on your board but until you characterize the noise itself, you may be chasing your own tail. The first thing I would do is test with the Electron modem OFF to see if that is the source to see if the noise disappears. Then, look at your signal path into the ADC.
Unless there is something I don’t know, the amount of RF design using an electron is virtually zero. It is all pre-done to the ufL connector.
As far as design to prevent interference into the I/O, that’s another matter and stitched ground planes will help. I really think you should consider a 4 layer board and eat the expense. Those big power and ground planes can help.
Is there a best practice for which layer is which in a >2 layer board? For a 4-layer board with top and bottom being ground, is it best to do a power and signal plane? Or is it best to have just a single ground and single power with 2 signal planes? I think that’s how the Electron is designed, right? power and ground in the middle with signal layers on the exterior?
Middle planes are usually ground and power with outer planes as signal.
So it’s been a while since this last post - had some time to re-design the board as a 4-layer board and fence analog lines as well as put the ADC’s closer to the inputs. However, there is still a huge issue whenever the Electron pushes to the cloud - it is manifested as a huge spike in our analog lines. I’m not actually sure it is RF interference, but maybe associated with the power draw from the Electron? I am powering using a 10W (5V, 2A) source that should be enough directly through VIN, and put in place the recommended caps, but it still seems to happen. Any suggestions on where to look next would be greatly appreciated!
I’ve taken screenshots of the board and schematic and can send them if needed.
Can’t read your latest schematic, but you don’t appear to have a separate PSU for the ADCs. I’d put a high PSRR LDO in there to feed them, to ensure that any power disturbances from the radio are attenuated as much as possible before they hit the ADC.
Given that these analog inputs come from off-board, it could also be that the wiring is picking up the noise, not the PCB. To prove this, make dummy plugs on an ADC input connector with resistor termination to ground (eg 100R) then try sending readings. If you don’t see the interference then it’s likely RF coupling onto your external wiring (another way to try this would be to use a long - maybe 2m - antenna cable and put the antenna as far as possible from the sensor wiring).
If the dummy plug shows no noise, then you’ll need to add some RF filtering on the ADC inputs; your interference is likely coming from RF picked up on the cables and then rectified by the ESD diodes on the ADC input pins.
Assuming the signals are all near DC, use a ferrite bead in series with each signal (as near the connector as possible, eg Murata BLM15GG471SN1 - the Murata SimSurfing tool will show you the impedance/frequency graph - click the “| Z |” button - you’re looking for something with high impedance in the cellular bands).
Also leave some space for 0402 footprints for capacitors to ground on the ADC side of the ferrite, which can be used to drop down what essentially are notch filters for problem frequencies; you look for a capacitor which has a low impedance at the trouble frequency to dump the signal to ground.