I2C interface timing [SOLVED]


OK sorry all - please ignore this if anyone actually saw the original thread…

I misread the data sheet and my own OLD PIC code (written years ago and then re-ported many times :-O).

I was using the WRONG address…


Did you try this onewire library - https://build.particle.io/libs/56d845c97a99d02037000508/ ?


Thread removed - TOTALLY my fault !!


Could you try this PR - https://github.com/spark/firmware/pull/856

Hi @mdma,

Sorry for an alarm caused - TOTAL brain failure on my part - using wrong chip address the 0x30 I have used for MANY years for this chip actually INCLUDES the write bit, as my old driver code didn’t actually shift it :-O. SHOULD be 0x18 - shifted up with write bit = 0x30…



Actually - belay that remark. Its NAKing me again :-((.

According to the I2C spec (NXP doc UM10204) SDA must be valid by the leading edge of SCL going high and remain so until SCL goes low. There is no specification for how long after SCL falls that SDA falls. In fact, if the next bit to send is another ‘1’, SDA may stay high until and during the next SCL clock.

Hi @GrahamS

I marked this as solved since you have edited your earlier posts to indicate that problem is fixed now.