Lost memory after publish?

[peekay123]

@GrahamS, as @tjp points out, disabling interrupts system wide is most likely causing some havoc with system firmware interrupts. Bit-banging 1-Wire is a pain due to the timing sensitivity and CRC errors are common. I'm not sure how often you get those errors.

In theory, it could be combined with DMA further reducing processor overhead. Maxim wrote an app-note on this.

Using a UART to Implement a 1-Wire Bus Master | Analog Devices

I also recall, a member used the USART for doing 1-wire communications.

Interrupt driven OneWire bus using USART hardware

I’ve written an implementation of the OneWire bus which uses the USART to offload all of the bus timing requirements on the hardware and is fully interrupt driven for read, write and search. The implementation follows Maxim’s App 214 - Using a UART to Implement a 1-Wire Bus Master. A compile time option for table based or bit-by-bit OneWire CRC provides a tradeoff between speed and code space utilization. An open drain drive circuit is required to adapt the push-pull TX output to the open drai…