@iitgrad , After an extensive discussion, we've determined that this is not a specific implementation of SPI we can support -- SPI itself still works as spec, and this is not a direct use of the peripheral.
It was the determination of our engineering team that the constraints imposed by the design are not really feasible for a device running RTOS code.
The recommendation remains to use a Serial based EEPROM, or an interposer chip if that's not possible.
The P2 also exposes a Pseudo EEPROM on flash if it's the only device that needs to access the memory. (Wear levelling is done by DeviceOS, and you can't reasonably wear out the flash)