Reading both clock and data line, faster reads possible?

I’m new so hopefully I’m putting this in the right place. I’m trying to spy on a data signal, so I have no latch, clock or data control, I can only watch. I used a Teensy 3.6 initially which was fast enough for this code, but I wanted to output the result of each latch to a UDP signal, so the Photon is the perfect device for this. The problem is, when I ported my code, the processor speed difference seems to be significant enough to miss reads or get out of sequence on the later reads. Is there a different way to do these types of reads, or am I going to have to do some pre-processing before it hits the photon? This is just changing LED state on every latch

if(pulseIn(A3, LOW)) { //latch

fart[0] = pinReadFast(A4); //data
pulseIn(A5, LOW); //clock
fart[1] = pinReadFast(A4); //data
pulseIn(A5, LOW); //clock etc
fart[2] = pinReadFast(A4);
pulseIn(A5, LOW);
fart[3] = pinReadFast(A4);
pulseIn(A5, LOW);
fart[4] = pinReadFast(A4);
pulseIn(A5, LOW);
fart[5] = pinReadFast(A4);
pulseIn(A5, LOW);
fart[6] = pinReadFast(A4);
pulseIn(A5, LOW);
fart[7] = pinReadFast(A4);

digitalWriteFast(D0, !fart[0]);
digitalWriteFast(D1, !fart[1]);
digitalWriteFast(D2, !fart[2]);
digitalWriteFast(D3, !fart[3]);
digitalWriteFast(D4, !fart[4]);
digitalWriteFast(D5, !fart[5]);
digitalWriteFast(D6, !fart[6]);
digitalWriteFast(D7, !fart[7]);


How about interrupts?

And there also is a brilliant tutorial by @rickkas7 who is reading the ADC for audio capture via timer interrupts

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To make sure I understand what you are trying to do:

  • On the falling edge of A3, you start getting samples.
  • On the falling edge of clock A5, you sample data A4.
  • You only take 8 samples.


  • Is the 8 samples all you need, or is that just for the example code?
  • The first sample is taken at the falling edge of A3, not the falling edge of A5. Is that intentional?

oh I was just looking at your async code yesterday rickkas!

Yes, just 8 samples total… first on the fall of A3, the remainder on the fall of A5. Missing the latch (A3) is acceptable sporadically so the digitalWrites to the LED pins or and UDP logic bogging down is fine, but once I catch a latch on A3, then I can’t miss anything on the clock (A5) or the data (A4) until the final (8th) data is received.

*edited, mislabeled a pin in explaination

I may be able to start my A4 read on the rising edge of the A5 clock signals, but the initially post-latch (A3) read still needs to be falling edge. I’m going to mess with that to see if that squeaks me by, but I think it’s actually relying on the signal and processor consistency that I’m not sure I can guarantee. Would be nice if there was a way to get all the reads in with some room to spare on either side of the clock movement though, so I’m still hoping someone can chime in with a miracle cure.