# Porting HT1632C driver to Spark Core, need help!

**URL:** <https://community.particle.io/t/porting-ht1632c-driver-to-spark-core-need-help/9239>\
**Category:** Firmware\
**Created:** [January 8, 2015, 11:12pm UTC](https://community.particle.io/t/porting-ht1632c-driver-to-spark-core-need-help/9239 "2015-01-08T23:12:59Z")\
**Posts on this page:** 2\
**Page:** 2

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**Author:** ![Catfang](https://sea2.discourse-cdn.com/flex026/user_avatar/community.particle.io/catfang/32/4210_2.png) [@Catfang](https://community.particle.io/u/Catfang)\
**Post date:** [February 12, 2016, 7:44pm UTC](https://community.particle.io/t/porting-ht1632c-driver-to-spark-core-need-help/9239/21 "2016-02-12T19:44:51Z")

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I was going to try the SPI version first, as it appeared to simplify the coding quite a bit.

Just to verify, from the HT1632C spec, I need three wires:  
CS / WR / DATA

HT1632C - Photon  
CS = SS (latch)\*1 ~ A2 (by default for SPI)  
WR = SLCK(?) ~ A3  
DATA = MOSI ~ A5

\*1 - I will have three of these in my implementation with 3 panels, A2, A6, A7

Do I at least have that part correct?

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**Author:** ![peekay123](https://sea2.discourse-cdn.com/flex026/user_avatar/community.particle.io/peekay123/32/810_2.png) [@peekay123](https://community.particle.io/u/peekay123)\
**Post date:** [February 13, 2016, 2:39am UTC](https://community.particle.io/t/porting-ht1632c-driver-to-spark-core-need-help/9239/22 "2016-02-13T02:39:01Z")

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@Catfang, software SPI is not really complicated but your pin assumptions for hardware SPI are correct with a CS line required for each panel “section”. The display uses SPI mode 0. Give it a shot and let me know how it goes!

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