Interrupts: #, priority, architecture

[ScruffR]

The docs state here

External interrupts are supported on the following pins:
Core: D0, D1, D2, D3, D4, A0, A1, A3, A4, A5, A6, A7
Photon: All pins with the exception of D0 and A5 (since at present Mode Button external interrupt(EXTI) line is shared with D0, A5). Also please note following are the pins for which EXTI lines are shared so only one can work at a time:
D1, A4
D2, A0, A3
D3, DAC
D4, A1

"All pins" include RX/TX (on the Core also)
And A pins are still fully capable digital pins.

@jim_hahn

Documentation says that once you are in an ISR, no other interrupts will occur.

Where does it say this, since it's not true (for all interrupts). The interrupt handling (including priorities and interrupting low prio ISRs in case of higher prio interrupts) is done by the µC according to its NVIC table (see datasheet p21f and ARM Cortex M3 specs)